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| CMCPCI102B CompactPCI(R) Backplane Interface Features * * * * * * * * * CompactPCI(R) standards compliant Allows CompactPCI System Cards to be used in any Slot Provides termination for up to ten channels Provides a series switch in each channel Supports hot-swap capability Very low capacitance load on each line Industrial temperature range 28-pin TSSOP package Lead-free version available Product Description The CMCPCI102BT/BR is a 10-channel backplane interface/termination IC specifically designed for CompactPCI redundant system-slot cards. The CMCPCI102BT/BR allows CompactPCI boards to interface to the backplane and provides the versatility to use system cards in any slot (system or peripheral). Per the CompactPCI specification, the CMCPCI102BT/ BR provides a 10 termination resistor for each channel to terminate the transmission line stub on the board. An integral series switch and associated control signal (SW_EN) permits connection/disconnection of the channel, so that the device side of the circuit may be isolated from the backplane side. The CompactPCI standard requires system boards to be hot-swappable. To accommodate this requirement, the CMCPCI102BT/BR features a switched 10k resistor connected to the 1V Precharge Supply Voltage. If the precharge enable pin (P_EN) is asserted, then the 10k pull-up resistors are connected to precharge the circuits. In addition, a system board requirement mandates either a 1.0k pull-up resistor or a 2.7k resistor connected to VIO. CompactPCI slot cards must work in either 3.3V or 5V systems, hence the need for both 2.7k and 1k resistors. If the 3_EN pin is logic high, the 2.7k resistor is used as the pull-up. If the 5_EN pin is logic high, the 1k resistor is used. The CMCPCI102BT/BR integrates all these functions in a low-profile 28-pin TSSOP package and is available with optional lead-free finishing. Applications * * * * * * * Redundant System CompactPCI(R) cards Hot-swap CompactPCI cards Industrial PCs Telecom/Datacom equipment Instrumentation Computer Telephony Real-time machine control Simplified Electrical Schematic 1V For all Enable signals: Logic 0 = switch open Logic 1 = switch closed *One of 10 parallel channels is shown. VIO 3_EN 5_EN SW_EN SWPU1 SWPU2 SWPU3 P_EN RPU1 10k RPU2 2.7k RS SWS RPU3 1k A1-A10* Backplane Side 10 CompactPCI Device Side B1-B10* (c) 2005 California Micro Devices Corp. All rights reserved. 02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 1 CMCPCI102B PACKAGE / PINOUT DIAGRAM Top View A1 A2 A3 A4 A5 1V P_EN GND CAP A6 A7 A8 A9 A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 B1 B2 B3 B4 B5 VIO 5_EN 3_EN SW_EN B6 B7 B8 B9 B10 Note: This drawing is not to scale. 28-pin TSSOP PIN DESCRIPTIONS PIN(S) 1-5 10-14 24-28 15-19 6 7 8 9 20 NAME A1 - A5 A6 - A10 B1 - B5 B6 - B10 1V P_EN GND CAP SW_EN DESCRIPTION The backplane-side input signals for channels 1 through 5, respectively. The backplane-side input signals for channels 6 through 10, respectively. The device-side connection for channels 1 through 5, respectively. The device-side connection for channels 6 through 10, respectively. A precharge supply voltage input for all channels. This voltage can be less than or equal to VIO. The precharge enable input which controls the precharge pull-up resistors. When this active high control signal is set to '1', the precharge of all channels is enabled. The ground voltage reference for the CMCPCI102BT/BR. A capacitor must be placed from this pin to GND. The recommended value is 0.01F,16V. The series switch enable input. When this active high control signal is set to '1', the series switch between the channel's backplane-side terminal and device-side terminal is closed. When this signal is cleared to '0', the switch is open. The enable signal for the device-side channel pull-up mechanism when 3.3V is the supply voltage. When this active high control signal is set to '1', the 2.7k pull-up resistor which pulls up the channel to the supply rail is engaged. Otherwise, this pin should be set to '0'. The enable signal for the device-side channel pull-up mechanism when 5V is the supply voltage. When this active high control signal is set to '1', the 1k pull-up resistor which pulls up the channel to the supply rail is engaged. Otherwise, this pin should be set to '0'. The positive supply voltage for the CMCPCI102BT/BR. Either 3.3V or 5V may be used. 21 3_EN 22 5_EN 23 VIO (c) 2005 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 02/28/05 CMCPCI102B Ordering Information PART NUMBERING INFORMATION Standard Finish Pins 28 Package TSSOP Ordering Part Number1 CMCPCI102BT Part Marking CPCI102B Lead-free Finish Ordering Part Number1 CMCPCI102BR Part Marking CPCI102BR Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER VIO (supply voltage) Pin Voltages 1V, P_EN, 3_EN, 5_EN, SW_EN A1-A10 B1-B10 ESD Withstand Voltage Human Body Model, MIL-STD-883D, Method 3015 (Notes 1, 2) Storage Temperature Range Operating Temperature Range (Ambient) DC Power per Resistor Package Power Rating RATING -0.5 to +6 -0.5 to (VIO+0.5) -0.5 to (VIO+0.5) -0.5 to (VIO+0.5) +2000 -65 to +150 -40 to +85 62 1 UNITS V V V V V C C mW W Note 1: ESD is applied to input / output pins with respect to GND, one at a time; unused pins are left open. Note 2: This parameter guaranteed by design. STANDARD OPERATING CONDITIONS PARAMETER VIO (supply voltage) Pin Voltages P_EN, 3_EN, 5_EN, SW_EN, 1V A1-A10 B1-B10 Ambient Operating Temperature Range RATING 3 to 5.5 0 to VIO 0 to VIO 0 to VIO -40 to +85 UNITS V V V V C (c) 2005 California Micro Devices Corp. All rights reserved. 02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 3 CMCPCI102B Specifications (Cont'd) ELECTRICAL OPERATING CHARACTERISTICS(NOTE 1) SYMBOL RS1 RS2 RPU1 TOLRPU2 TOLRPU3 TCRPU C1 C2 PARAMETER Series Resistance through RS Series Resistance through RS Resistance of RPU1 pull-up Resistance Tolerance (RPU2 and RPU3) Temperature Coefficient of Resistance (RPU1, RPU2, RPU3) Capacitance on backplane side (A side) of series resistor RS Capacitance on device side (B side) of series resistor RS and series switch SWS Logic Low Input Voltage to P_EN, 3_EN, 5_EN, SW_EN Logic High Input Voltage to P_EN, 3_EN, 5_EN, SW_EN Leakage Current into P_EN, 3_EN, 5_EN, SW_EN Supply Current for internal circuits (measured at GND pin) Switch SWS closure delay from the low-to-high transition of SW_EN Note 2, 'CAP' pin capacitor=0.01F GND < V < VIO Measured @ 66MHz, 0VDC, SW_EN=0V; Note 2 Measured @ 66MHz, 0VDC, VIO=5V, 5_EN=5V SW_EN=0V; Note 2 -0.5 [VIO] x 0.7 +1 0.25 14 12 10 CONDITIONS A to B; switch SWS closed; TA=25C A to B; switch SWS open; TA=25C TA=25C TA=25C MIN 5 1 9.5 18 +5 TYP 10 MAX 15 UNITS M k % -100 1.9 4.2 ppm/C pF pF VIL VIH ILEAK IGND tPLH tPHL tPPU [VIO] x 0.3 [VIO] + 0.5 +10 1 V V A mA ms s ns Switch SWS delay from the high-to- Note 2, 'CAP' pin capacitor=0.01F low transition of SW_EN Propagation delay for pull-up switches SWPU1, SWPU2, and SWPU3, all transitions Note 2 Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. Note 2: This parameter is guaranteed by design; it is not tested 100%. (c) 2005 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 02/28/05 CMCPCI102B Performance Information CAP Pin Capacitance Resistance Variation with Input Voltage The series resistance RS varies with input voltage and supply voltage, as shown in Figure 1. Variation of 10R Resistor with I/O Voltage, T=25'C 15 14 13 12 Vcc5.5 Vcc3.0 Some external capacitance is necessary to prevent the voltage on the CAP pin from falling during sustained data transfers through the device. This ensures that the logic 1 level does not degrade. The time required to open and close the series switch, SWs, varies according to how much capacitance is present on the CAP pin. The minimum usable value is 200pF, placed close to the pins. A 0.01uF, 16V capacitor is recommended. See Figure 3 and Figure 4 for variation of switch on/off times vs. capacitance. Switch ON Time vs. CAP Capacitor Value 16 Resistance [ ] 11 10 9 8 7 6 5 0 1 2 3 I/O Voltage [ V ] 4 5 6 14 12 Figure 1. Resistance Variation vs. Input Voltage SWs Closing Tim e [mS] 10 8 6 4 2 0 0 2000 4000 6000 8000 10000 12000 Capacitor Value on CAP Pin [pF] Resistance Variation with Temperature The series resistance RS also varies with temperature, as shown in Figure 2. Temperature Variation of 10R Resistor 15 14 13 12 VCC5VIN0 VCC5VIN5 VCC3VIN0 VCC3VIN3 Figure 3. Switch ON Time vs. CAP Capacitor Value Switch OFF Time vs. CAP Capacitor Value 14 12 10 8 Resistance [ ] 11 10 9 8 7 6 5 -40 -20 0 20 40 60 80 100 SWs Opening Tim e [S] Temperature [ oC ] 6 4 2 0 0 2000 4000 6000 8000 10000 12000 Capacitor Value on CAP Pin [pF] CONDITIONS: Curve VCC3VIN0: Curve VCC3VIN3: Curve VCC5VIN0: Curve VCC5VIN5: VIO = 3.0V VIO = 3.0V VIO = 5.5V VIO = 5.5V channel voltage = 0.0V channel voltage = 3.0V channel voltage = 0.0V channel voltage = 5.5V Figure 2. Resistance Variation vs. Temperature Figure 4. Switch OFF Time vs. CAP Capacitor Value (c) 2005 California Micro Devices Corp. All rights reserved. 02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 5 CMCPCI102B Performance Information (cont'd) Capacitance Variation with Frequency The A-side and B-side capacitances, C1 and C2, will vary with frequency. The backplane capacitance, C1, is very linear over a wide frequency range. Figure 5 shows a plot of input line A3 (pin 3), measured with SW_EN=0V and VIO=5V. Figure 5. C1 (Backplane-side) Capacitance Variation vs. Frequency The CompactPCI device side of the CMCPCI102BT/ BR has a fairly low capacitance (C2) at 66MHz, but it is higher at lower frequencies. Figure 6 shows a plot of output line B3 (pin 26), measured at the worst-case (for capacitance) conditions of SW_EN=0V, 5_EN=0V, 3_EN=0V and VIO=5V. The increased capacitance at low frequencies is due to the parasitic capacitance of the switches connected to the pull-up resistors. At high frequencies, this parasitic capacitance is decoupled by the pull-up resistors. Figure 6. C2 (Device-side) Capacitance Variation vs. Frequency (c) 2005 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 02/28/05 CMCPCI102B Application Information Board Layout Recommendations The CMCPCI102BT/BR devices should be located on the board as close as possible to the CompactPCI connector. Whether a signal is terminated or not depends upon application, as shown in the following table: SIGNAL(S) SYSTEM SLOT BOARDS 32-Bit AD0-AD31 C/BE0#-C/BE3# PAR FRAME# IRDY# TRDY# STOP# LOCK# DEVSEL# PERR# SERR# RST# REQ64# ACK64# INTA#, INTB#, INTC#, INTD# (if used) AD32-AD63 C/BE4#-C/BE7 PAR64 terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate N/A N/A N/A 64-Bit terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate terminate * * Figure 7 shows a 64-bit system board connection between the CMCPCI102BT/BR termination and the CompactPCI 5-row connector (2 mm pitch) labeled A to E (row F is Ground). The System slot should have signal lengths not exceeding 63.5 mm (2.5 inches). To minimize trace length, it is recommended that the CMCPCI102BT/BRs be placed on alternate sides of the PC board. The configuration shown illustrates a fully-terminated 64-bit board utilizing 10 CMCPCI102BT/BR devices. Some applications (e.g. 32-bit boards) do not require all lines to be terminated, per the above table. The CMCPCI102BT/BR resistors have a very low TCR (typically -100ppm/C) so that resistance will not fluctuate over temperature. Buffers are implemented on P_EN, 5_EN and 3_EN inputs to ensure that switches turn on and off completely. A typical system slot card may use 10 CMCPCI102BT/ BR devices to replace 10 10-bit FET bus switches and 76 4-resistor packs (0805 form factor), thus providing significant reduction in both component count and assembly costs. At the same time this highly integrated solution improves reliability and manufacturing efficiency, saves board area for space-critical designs, and satisfies CompactPCI height requirements. * * * Placed on bottom side of PC board * Figure 7. Schematic for 64-bit System Board (c) 2005 California Micro Devices Corp. All rights reserved. 02/28/05 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 7 CMCPCI102B Mechanical Details TSSOP Mechanical Specifications CMCPCI102BT/BR devices are supplied in 28-pin TSSOP packages. Dimensions are shown below. For complete information on the TSSOP-28 package, see the California Micro Devices TSSOP Package Information document. 28 27 26 25 24 23 Mechanical Package Diagrams TOP VIEW D 22 21 20 19 18 17 16 15 PACKAGE DIMENSIONS Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min -- 0.05 0.19 0.09 9.60 4.30 6.25 0.50 Max 1.10 0.15 0.30 0.20 9.80 4.50 6.50 0.70 Min -- 0.002 0.0075 0.0035 0.378 0.169 0.246 0.020 TSSOP 28 Inches Max 0.0433 0.006 0.0118 0.0079 0.386 0.177 0.256 0.028 C SEATING PLANE SIDE VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 H Pin 1 Marking E A B e A1 0.65 BSC 0.0256 BSC END VIEW 50 pieces* 1000 pieces L Controlling dimension: millimeters * This is an approximate number which may vary. Package Dimensions for TSSOP-28 (c) 2005 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 02/28/05 |
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